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Ronak Singhal
CPU architect. Intel Fellow. CMU alumnus. Pittsburgh in the blood.
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Ronak Singhal proslijedio/la je tweet
JOE MANGANIELLO 2. velj
Man, I’m ready to run through a wall after watching this...
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Ronak Singhal 20. sij
Odgovor korisniku/ci @LisaSpelman @OregonZoo
Looks like one of the eagles at the ?
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Ronak Singhal 17. pro
Odgovor korisniku/ci @_msw_ @Liran_Alon
You may want to look at the CLDEMOTE instruction coming in future HW. Then you could do a store+CLDEMOTE to get behavior similar to what you are looking for.
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Ronak Singhal 17. pro
Odgovor korisniku/ci @_msw_ @Liran_Alon
Correct that today there is no instruction that allows you to directly place data in a particular cache level like you describe. In general, cache management via software is hard (my opinion is similar with SW prefetching although that is starting to become more mature finally).
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Ronak Singhal 17. pro
Odgovor korisniku/ci @Liran_Alon
The first table you quoted (2-28) is for Sandy Bridge. On Skylake, look at Table 2-12. Still 4 entries in the 1st level DTLB but now backed by 16 entries in the STLB. On paging structure cache entries -- those are separate structures above and beyond what is shown in the TLBs.
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Ronak Singhal 5. pro
Odgovor korisniku/ci @lemire
Are the values in the second chart reversed?
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Ronak Singhal 2. pro
Odgovor korisniku/ci @jonmasters
We can give a whole treatise on how they differ....
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Ronak Singhal 22. stu
Odgovor korisniku/ci @handleym99 @ashokraj
See section 3.6 of the spec on how completion is communicated: On performance -- that is implementation dependent (including what the perf of mem* is on whatever is the core of interest), so wait for the first implementation :)
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Ronak Singhal proslijedio/la je tweet
ashokraj 20. stu
Read the intro blog, code should hit upstream today. Something we have been working on for a while. Introducing the Intel® Data Streaming Accelerator (Intel® DSA)
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Ronak Singhal 19. stu
Deep and long pool of water on Brookwood heading south towards Cornell, right by the library. Was very dangerous about 10 minutes ago. No signs warning of high water.
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Ronak Singhal 14. stu
Odgovor korisniku/ci @ScottKacsmar
Hmmm....Ben-->AB in the PIT-JAX 2017 WC was > 35:
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Ronak Singhal 5. stu
This document is a Runtime Optimization Blueprint illustrating how the performance of runtimes can be improved by using large code pages. The intended audience are runtime implementers, and customers/providers deploying runtimes at scale.
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Ronak Singhal proslijedio/la je tweet
Intel News 25. lis
Why more software development needs to go to the machines:
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Ronak Singhal 19. lis
Odgovor korisniku/ci @jonmasters
I think it means they should check if they have a TSC bug
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Ronak Singhal proslijedio/la je tweet
Mike Burrows 9. lis
We help a lot of game devs and are always humbled by their feedback. We asked if we could record some of them and their experiences. Here’s a few: Kudos to , David Fortner and
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Ronak Singhal 7. lis
Odgovor korisniku/ci @trav_downs @geofflangdale
It is 12-ways. We need to correct.
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Ronak Singhal proslijedio/la je tweet
Gregory M Bryant 2. lis
The innovation we’ve achieved with Lakefield gives our partners the ability to deliver new experiences. The Neo is an incredible example.
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Ronak Singhal 2. lis
Odgovor korisniku/ci @rivet_amber @geofflangdale
yes
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Ronak Singhal 30. ruj
Odgovor korisniku/ci @geofflangdale
Figure 2-1 in the opt guide shows general port assignments
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Ronak Singhal 28. ruj
Odgovor korisniku/ci @DROP_ALL_TABLES @IanCutress i 4 ostali
Again, just to be pedantic, this is tied to the P state being requested by the OS. Not about different cores having different capabilities. So, if one core is at P1 and another at Pn, they can run at different f and v.
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