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Ronak Singhal
@
rsinghal1
Portland, OR
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CPU architect. Intel Fellow. CMU alumnus. Pittsburgh in the blood.
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421
Tweetovi
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2.986
Pratim
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876
Osobe koje vas prate
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JOE MANGANIELLO
@JoeManganiello
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2. velj |
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Man, I’m ready to run through a wall after watching this... #HereWeGo @steelers twitter.com/steelers/statu…
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Ronak Singhal
@rsinghal1
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20. sij |
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Looks like one of the eagles at the @OregonZoo?
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Ronak Singhal
@rsinghal1
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17. pro |
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You may want to look at the CLDEMOTE instruction coming in future HW. Then you could do a store+CLDEMOTE to get behavior similar to what you are looking for.
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Ronak Singhal
@rsinghal1
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17. pro |
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Correct that today there is no instruction that allows you to directly place data in a particular cache level like you describe. In general, cache management via software is hard (my opinion is similar with SW prefetching although that is starting to become more mature finally).
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Ronak Singhal
@rsinghal1
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17. pro |
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The first table you quoted (2-28) is for Sandy Bridge. On Skylake, look at Table 2-12. Still 4 entries in the 1st level DTLB but now backed by 16 entries in the STLB. On paging structure cache entries -- those are separate structures above and beyond what is shown in the TLBs.
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Ronak Singhal
@rsinghal1
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5. pro |
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Are the values in the second chart reversed?
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Ronak Singhal
@rsinghal1
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2. pro |
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We can give a whole treatise on how they differ....
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Ronak Singhal
@rsinghal1
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22. stu |
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See section 3.6 of the spec on how completion is communicated: software.intel.com/sites/default/…
On performance -- that is implementation dependent (including what the perf of mem* is on whatever is the core of interest), so wait for the first implementation :)
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ashokraj
@ashokraj
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20. stu |
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Read the intro blog, code should hit upstream today. Something we have been working on for a while. Introducing the Intel® Data Streaming Accelerator (Intel® DSA) shar.es/a3gIo9
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Ronak Singhal
@rsinghal1
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19. stu |
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@washcoroads Deep and long pool of water on Brookwood heading south towards Cornell, right by the library. Was very dangerous about 10 minutes ago. No signs warning of high water.
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Ronak Singhal
@rsinghal1
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14. stu |
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Hmmm....Ben-->AB in the PIT-JAX 2017 WC was > 35: espn.com/nfl/game?gameI…
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Ronak Singhal
@rsinghal1
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5. stu |
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This document is a Runtime Optimization Blueprint illustrating how the performance of runtimes can be improved by using large code pages. The intended audience are runtime implementers, and customers/providers deploying runtimes at scale. software.intel.com/en-us/articles…
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Intel News
@intelnews
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25. lis |
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Why more software development needs to go to the machines: intel.ly/2JmxnKY pic.twitter.com/gqoX5IYVNh
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Ronak Singhal
@rsinghal1
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19. lis |
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I think it means they should check if they have a TSC bug
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Mike Burrows
@zebedee666
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9. lis |
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We help a lot of game devs and are always humbled by their feedback. We asked if we could record some of them and their experiences. Here’s a few:
software.intel.com/en-us/videos/i…
@Rajaontheedge @jimkxa @IntelGraphics @IntelGaming
Kudos to @Phil30397981, David Fortner and @Intel_Steve
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Ronak Singhal
@rsinghal1
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7. lis |
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It is 12-ways. We need to correct.
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Gregory M Bryant
@gregorymbryant
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2. lis |
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The innovation we’ve achieved with Lakefield gives our partners the ability to deliver new experiences. The @surface Neo is an incredible example. #MicrosoftEvent #SurfaceEvent #IamIntel newsroom.intel.com/news/microsoft…
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Ronak Singhal
@rsinghal1
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2. lis |
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yes
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Ronak Singhal
@rsinghal1
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30. ruj |
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Figure 2-1 in the opt guide shows general port assignments
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Ronak Singhal
@rsinghal1
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28. ruj |
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Again, just to be pedantic, this is tied to the P state being requested by the OS. Not about different cores having different capabilities. So, if one core is at P1 and another at Pn, they can run at different f and v.
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