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RISC-V
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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RISC-V 40 min
The Foundation’s next stop is Nuremberg, Germany to attend . Be sure to stop by Hall 3A and booth 3A-536 to see 14 pod exhibits representing member companies and presentations featuring its technology. Register here:
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RISC-V 31. sij
. has successfully verified its first line of processors, called NOEL-V™, using Riviera-PRO™ for mixed-HDL simulation. Learn more:
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RISC-V 31. sij
Big shout-out to for demoing running on at the "Linux on and systemd-homed" Meetup in Chicago last week. Check out his column in the latest on how is enabling open source design:
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RISC-V 30. sij
. appointed former and engineer Chris Lattner to lead ’s Platform Engineering, which leverages design methodology for customizable chips:
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RISC-V 30. sij
In her keynote presentation at the 2019 Hackaday Superconference last week, VP of Engineering Dr. Megan Wachs gave an introduction to the . check out this video of her talk and an interview with :
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RISC-V proslijedio/la je tweet
CNX Software 26. sij
Open-source platform to design or based SoC's running on 's and implementing open source accelerators such as NVDLA.
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RISC-V proslijedio/la je tweet
SiFive 24. sij
Yunsup Lee, CTO of SiFive, spoke at the 2019 summit about taking into new markets. Watch the full video at the link below and see how SiFive is empowering by leading the development of a broad ecosystem.
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RISC-V proslijedio/la je tweet
Calista Redmond 24. sij
This article is worth every word validating the appetite and investment in from tech giants spanning industries. Open silicon is not the future, it is now.
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RISC-V 29. sij
. at covered ’s announcement that it is using for its processor and future implementations. Read more:
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RISC-V 29. sij
. is presenting a workshop at on how to properly implement secure systems. If you are attending, check out his talk on Feb. 25, 2020 from 2:30-4 p.m.
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RISC-V 28. sij
At FOSDEM 2020 next week, Computer Science Professor Luca Carloni is presenting on how the ESP open source platform for systems-on-chips integrate hardware accelerators:
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RISC-V 28. sij
. hosted the first Isreali dedicated entirely to technology. Highlights from the event at can be found here:
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RISC-V 27. sij
Last Monday, Jeremy Bennett at presented the Student of the Year Award to Florin Blanaru at the London Open Source Meetup, hosted by and the Open Source Hardware User Group:
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RISC-V 27. sij
Did you know the ISA can optimize high-bandwidth communication between cores and DSAs? If not, read up on ’s blog post to learn more:
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RISC-V 27. sij
the Summit 2019 delved into the latest implementations of technology. Check out the full playlist of presentations from the event on the Foundation’s channel:
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RISC-V 24. sij
Join us at the "Linux on and systemd-homed" Meetup tomorrow at 2 p.m. at Pumping Station: One in Chicago, where will demo Linux running on on the Hackaday Supercon Badge. RSVP here:
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RISC-V 24. sij
In the latest episode of ’s Amelia Dalton’s Fish Fry podcast, she describes a variety of design trends for 2020, including the rise of . Tune in here:
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RISC-V proslijedio/la je tweet
DeRISC EU Project EIC-FTI 869945 22. sij
Today we show to the audience through our poster . Don't hesitate to contact us to ask about the project! And thanks to for being there the whole day to solve questions!
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RISC-V 24. sij
. at Bloomberg explores how is revolutionizing the chip industry. Learn more about how the Foundation’s ecosystem is building an open source movement:
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RISC-V 23. sij
French company is developing processors for supercomputers, AI and cars using cores as part of the (article in German):
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