Twitter | Search | |
Search Refresh
All About Circuits Aug 30
Discover registers.
Reply Retweet Like
John W Woolsey Aug 30
Interested in designing and implementing custom digital circuits in Verilog on an FPGA? Check out Woolsey Workshop's new tutorial. Getting Started With The TinyFPGA BX
Reply Retweet Like
migry Sep 2
So here is the first time I have seen the boot screen. Clearly the arbitration between video and CPU access is not working. Back to the source. Part of my "Karen" with project.
Reply Retweet Like
LOS Sep 18
About to start teaching myself the fundamentals of the language. If anyone has any pointers or resources to share I would be very grateful.
Reply Retweet Like
AnySilicon Jan 21
Reply Retweet Like
Electronics SE Sep 19
How to assign value to bidirectional port in verilog?
Reply Retweet Like
Antmicro Sep 10
Co-simulate your IP with and - plug in a peripheral under development to an entire system running and test a real-world use case. Read our blog note and see the demo on GitHub:
Reply Retweet Like
Rob Kemp Sep 13
Come join the Next Generations Standards (NGS) team here at JR0104126 5G Modem RTL Design Engineer; Santa Clara, CA:
Reply Retweet Like
Andreas Kahler Aug 22
Thanks for the workshop today, and ! So many cool new things (for me) to start experimenting with!
Reply Retweet Like
Juan Ordoñez Cerezo Dec 5
Controlling a RC transmitter via hardware —> FPGA
Reply Retweet Like
Ben Morse Mar 7
Just fixed a valid ready bug and even avoided a 32 bit compare. Feeling so good
Reply Retweet Like
Xavier Martin Jan 16
I wish I would have discovered earlier, when I was student for instance. This sand box is really useful for fast prototyping, sharing Code with others and more...
Reply Retweet Like
ByteSnap Sep 17
Reply Retweet Like
Electronics SE Sep 17
Generate an n bit random number in Verilog
Reply Retweet Like
Michael Field Feb 23
I've uploaded my IP-free Implementation to a new repo. Feel free to take a look around, and try it on your board. My Verilog skills are weak, so any help would be greatly received.
Reply Retweet Like
Panda Spirit Jul 2
+you can't use for() in ! -keep calm and do it by generate :)
Reply Retweet Like
Dr Simon Monk Mar 22
My book in Chineese - I think.
Reply Retweet Like
@uint8_t@chaos.social Dec 31
After the workshop I'm trying to dive into programmable logic and learn and bumped into this awesome website which I would hereby recommend to everyone interested in HDL.
Reply Retweet Like
Ross McKinlay Apr 18
Does the thought of VERILOG make you want to cry? Do you continually dream of programming hardware for an using RACKET MACROS? Well now's your chance with my new work-in-progress language FAIRYLOG!
Reply Retweet Like
Steckschwein Apr 30
Which CPLD to use? Lattice ispMach 4A: easily availiable, 150€ programmer, Lattice ISPlever is Windows only Xilinx XC95nn: harder to come by, dead cheap programmer, Xilinx ISE runs on Linux
Reply Retweet Like