Twitter | Search | |
Search Refresh
Agnisys 8h
Getting right for your is a difficult engineering & challenge with very high stakes.
Reply Retweet Like
AgileAnalog 11h
Too much flexiblity in can be a liability rather than the key to success according to . Get Analog that matches your exact requirements at
Reply Retweet Like
ImperasSoftware Jul 11
Simon Davidmann, Imperas CEO Joins Jim Hogan’s panel at ES Design West, "Are we Experiencing a Renaissance in Chip Design and EDA?" with Joe Costello and Execs from Metrics, Breker, One Spin, and Methodics
Reply Retweet Like
eInfochips (An Arrow Company) Jul 16
Wanna do silicon design layout & RTL to GDSII Services at 16nm technology & below? Get in touch:
Reply Retweet Like
6SigmaET Jul 11
Tired of thermal simulation tools that can’t model in the same level of detail as your 2.5D EDA tool? Look no further, the Package Builder can maintain detail across toolsets and system level models:
Reply Retweet Like
AgileAnalog Jul 17
In , there are now many factors to balance, described by as a maze of tradeoffs: power, performance, area, security and safety  
Reply Retweet Like
AgileAnalog Jul 18
’s report looks at the players striving to lead in the chip design race. believes it’s all about partnerships and embracing the ecosystem
Reply Retweet Like
Cadence India Jul 10
In this week’s , Shrinivas tells us all about the SLAM algorithm and the importance of Vision Q7 DSP for your Vision and AI SoC. What did you take away from this session of ?
Reply Retweet Like
schekeb fateh Mar 4
Reply Retweet Like
Mayank Sharma Feb 21
Reply Retweet Like
efabless.com Jun 13
X-Fab & Efabless Announce Raven Open-source RISC-V SoC --
Reply Retweet Like
Marin Goleminov Jun 28
Reply Retweet Like
brad hobbs May 27
Reply Retweet Like
Infoxeron Technologies Dec 3
Intel Acquires Indian Entrepreneurs’ Startup Netspeed Systems for Chip Design... For More Detail click on the link
Reply Retweet Like
ASE Group Jan 9
What a fantastic from AMD CEO Lisa Su at who immediately highlighted new approaches to , namely heterogeneous integration. That’s ASE’s specialty - and it’s clearly enabling higher and higher performance applications.
Reply Retweet Like
Satyam Singh May 7
It's a good read on challenges involve in open source chip design.
Reply Retweet Like
Learn Steps Dec 23
Reply Retweet Like
Semiconductor Engineering Jun 22
Semiconductor Engineering .:. Week In Review: Design, Low Power
Reply Retweet Like
AgileAnalog Jul 11
Reply Retweet Like
SOI Consortium May 13
We're teaming up with our members on two great events in China this month, including a TrainingDay in Shanghai
Reply Retweet Like