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David Shah
Linux on an mor1kx based SoC with 32MB SDRAM built using an end-to-end FOSS flow - FuseSoC, Yosys, nextpnr and Trellis, targeting the ULX3S ECP5 board. Many thanks to and for their help with debugging.
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David Shah Oct 19
Replying to @fpga_dave
The Linux "heartbeat" function makes for a very nice blinky!
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Dimitar Tomov Oct 19
Replying to @fpga_dave
It's by design 😁 Good job, Dave!
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Olof Kindgren Oct 19
Replying to @fpga_dave
Now I'm of course curious to know what the problem was that had the code hanging during the MMU init
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David Shah Oct 19
Replying to @OlofKindgren
Yosys was wiping out one of the read ports of the TLBs... . Not sure why it was also failing in simulation - seems to be a different problem that looked similar, I think to do with Xs somewhere they shouldn't be.
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Olof Kindgren Oct 19
Replying to @fpga_dave @alt_kia
Well spotted! I can take a look at the simulation issues once I have taken care of the infrastructure stuff
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David Shah Oct 19
Replying to @fpga_dave
You can also make a blinky using the BusyBox shell!
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Stafford Horne Oct 19
Cool! It looks like an old version of openrisc Linux. Let me know if you need help running an upstream kernel. Or if you have instructions / fusesoc cores I would like to try it out.
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Olof Kindgren Oct 19
I've upstreamed the dependencies (really only a new version of wb_sdram_ctrl needed) and am working on modernizing the SoC. You can find my WIP here
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Kia‏☆ Oct 19
how did you find this bug, i'm curious?
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David Shah Oct 19
I went with the older kernel for now because it seemed to be more tried and tested with the de0_nano example this was based on. I'll try my config and dts with the newer kernel soon. Also would like to try building the rootfs from scratch.
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David Shah Oct 19
Replying to @alt_kia @OlofKindgren
Used gdb via openocd&JTAG to single step and inspect registers. Doing this I could see that the TLB match register writes weren't taking effect so there was a TLB miss loop. Then I inspected the netlist and saw that one read port had disappeared compared to the source.
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David Shah Oct 19
Replying to @alt_kia @OlofKindgren
Then took the TLB code and turned it into a minimised example to debug what was going on inside Yosys by inspecting the design at various points in the flow.
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David Shah Oct 20
Tried the latest mainline kernel and it pretty much "just works" with my existing defconfig and dts - just needed to use your or1k-utils initramfs! Only problem I notice is that the LEDs aren't working in Linux any more, probably some driver change.
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Stafford Horne Oct 20
Great. I think it's because upstream doesn't have the gpio "jbtrivial" driver yet. I would need to rename it to take it upstream. But I was thinking maybe there is an alternative gpio ip core / driver.
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Warren Toomey Dec 10
Replying to @fpga_dave
David, is there a repo for this? I have an ULX3S board & would love to bring Linux up on it.
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David Shah Dec 10
Replying to @DoctorWkt
The main fusesoc project for the or1k SoC is here: . The kernel is here: . SPI boot doesn't work, so you'll have to load the kernel using OpenOCD and a second JTAG adapter on some FPGA pins.
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Marius Slavescu Jan 1
Would be possible to port this on ECP5 Embedded Vision Kit? Also on based board. See both boards here: Would love to use it for smart camera!
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Olof Kindgren Jan 1
Should be straight-forward to do. There are linux-capable OpenRISC SoCs available for several Xilinx boards already. I'm using it also on Altera boards for automotive RADAR processing on Altera boards at my day job :)
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