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@daniel_bilar | |||||
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#apsys aISA: Augmented ISA for timing channel protection ts.data61.csiro.au/publications/c… #spectre
[prime-n-probe multi-gen x86 & ARM study: each contains microarch state exploitable as timing channel, but cannot be reset architected mechanisms; see ERI pushes twitter.com/daniel_bilar/s… ] pic.twitter.com/bBPLnG9TMY
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Harvester
@Harvesterify
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29. kol 2018. |
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Will have to read this one carefully.. :-)
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