|
@Liran_Alon | |||||
|
I also wonder how these entries are separated between "translation entries" and "paging-structure-cache entries". I didn't find this information specified anywhere. I do hope these numbers don't include the latter and that there are additional entries for that somewhere. :) (2/2)
|
||||||
|
||||||
|
Liran Alon
@Liran_Alon
|
17. pro |
|
Surprised by interesting numbers in Intel Optimisation Guide section 2.5.5.2 L1 DCache. Turns out there are only 4 DTLB entires for 1GB pages! Crazy! So mapping all guests memory as 1GB pages in EPT may be less efficient? Worth benchmarking! @_msw_ @Karim_Allah @rsinghal1 (1/2) pic.twitter.com/wmlyFJBp8z
|
||
|
|
||
|
Ronak Singhal
@rsinghal1
|
17. pro |
|
The first table you quoted (2-28) is for Sandy Bridge. On Skylake, look at Table 2-12. Still 4 entries in the 1st level DTLB but now backed by 16 entries in the STLB. On paging structure cache entries -- those are separate structures above and beyond what is shown in the TLBs.
|
||
|
|
||
|
Liran Alon
@Liran_Alon
|
17. pro |
|
Oh my bad. I missed that. Thanks! This makes more sense. :) Does Intel have plans to publish numbers on amount of paging-structure-cache entries?
|
||
|
|
||